【摘要】 本文提出了一种64×4扫描型红外焦平面读出电路。电路采用0.5μm标准CMOS工艺。工作电压为5V。本设计在列读出级采用了降低寄生电容影响的设计,以降低电路输出相对无寄生电容设计输出值的偏差,提高各通道的一致性。在对具有4级TDI、微扫描步长为探测器中心间距1/3的读出电路列暂存级进行的仿真中,相对于改进前的普通电路结构,本文提出的新型电路结构与设计理想值之间的偏差降为原来的10%。更多还原

【Abstract】 In this paper,a novel 64×4 scanning IRFPA(Infrared Focal Plane Array)readout integrated circuit is proposed.The circuit is made by a standard 0.5μm CMOS process and operates at the voltage of 5V.In order to reduce the output deviation due to the parasitic capacitance and improve the uniformity of signal channels,a low parasitic capacitance effect design is used in the column readout stage of the circuit.A column readout stage which has a four-stage TDI(Time Delay Integration)and a scanning step length of one-third of the detector pitch is simulated.The simulation result has shown that the output deviation of this novel circuit structure is reduced by a factor of 10% compared with that of the original column readout stage.更多还原