【摘要】 设计了一种低功耗的2D DCT/IDCT处理器。为了降低功耗,设计基于行列分解的结构,采用了Loeffler的DCT/IDCT快速算法,并使用了零输入旁路、门控时钟、截断处理等技术,在满足设计需求的基础上降低了系统的功耗。常系数乘法器是该处理器的一个重要部件,文中基于并行乘法器结构设计了一种新型的低功耗常系数乘法器,它采用了CSD编码、Wallace Tree乘法算法,结合采用了截断处理、变数校正的优化技术,使得2D DCT/IDCT处理器整体性能有较大提高。设计的时钟频率为100 MHz,可以满足MPEG2 MP@HL实时解码的应用。采用SMIC0.18μm工艺进行综合,该2D DCT/IDCT处理器的面积为341 212μm2,功耗为14.971 mW。通过与其他结构的2DDCT/IDCT处理器设计分析与比较,在满足MPEG2 MP@HL实时解码应用的同时,实现了较低的功耗。更多还原

【Abstract】 In this paper a low power 2D DCT/IDCT processor is presented.This processor uses Loeffler’s fast algorithm to reduce the power consumption.In addition,zero bypassing,clock gating and truncation are used to reduce the switching activities and the power consumption.Constant coefficient multiplier is a very important part of 2D DCT/IDCT processor.This paper also presents a low power and constant coefficient multiplier with CSD coding and Wallace Tree addition algorithm.The multiplier adopts truncation and variable correction technologies which improve the performance of 2D DCT/IDCT processor significantly.The 2D DCT/IDCT processor is synthesized in SMIC 0.18 μm Technology.The proposed design has a measured power dissipation of 14.971 mW and area of 341 212 μm2 at 100 MHz.It is more power-efficient than other previously reported 2D DCT/IDCT processor designs.更多还原