【摘要】 提出一种采用列共用模拟重构电路和双积分三采样工作时序的CMOS图像传感器(CIS)系统架构,可实现光电响应曲线压缩和像素固定模式噪声(FPN)消除,提高传感器动态范围到83dB,使成像质量提高。该结构具有与单采样相同的像素阵列,仅增加很小的处理电路。改进的工作时序优化了长积分、短积分和信号处理的时序分配。系统控制由FPGA实现。功能和数模混合仿真验证表明,方案是可行的。更多还原

【Abstract】 Based on column-level analog reconstruction and control sequence of dual-integration-three-sampling.A CMOS imager sensor(CIS) system is presented,which realizes a compression of the illumination to charge transfer curve,avoids the fixed pattern noise(FPN) in the pixel,and improves the dynamic range ot 83 db for imaging quality.This architecture has a small extra processing circuit and the same pixel array as single sampling.Improved timing control method optimizes the timing distribution between long integration,short integration and signal processing.The system control is implemented with FPGA.The function and mixed signal verification confirms the feasibility of this design.更多还原