【摘要】 高速ADC、DAC对时钟质量的要求越来越高.对此介绍了一种基于时钟同步器与抖动清除器CDCM7005的低抖动时钟设计.并分析了时钟抖动对信噪比的影响及抖动的计算,介绍了在WCDMA数字中频系统中CDCM7005的具体设计应用,引入了SignalTap这种新的测试方法,最后测试了时钟性能,计算了时钟相位噪声、抖动值和ADC的信噪比,整体指标达到设计要求.更多还原

【Abstract】 The requirement of clock’s quality in ADC、DAC system increased quickly.A new low jitter method which based on Clock Synchronizer and Jitter Cleaner CDCM7005 was proposed.We analysed the relationship between clock jitter and SNR,and introduced the calculation of jitter.The application of CDCM7005 in WCDMA digital Intermediate Frequency system was presented.And a new testing method which used SignalTap was introduced.At last,we tested the performance of clock,calculated the jitter of clock、phase noise and ADC’s SNR.The quality of clock met the system requirements well.更多还原