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低压中和化CMOS差分低噪声放大器设计
Design of a Low Voltage Neutralized CMOS Differential Low Noise Amplifier
【摘要】 以设计低电压LNA电路为目的,提出了一种采用关态MOSFET中和共源放大器输入级栅漏寄生电容Cgd的CMOS差分低噪声放大器结构.基于该技术,采用0.35μmCMOS工艺设计了一种工作在5.8GHz的低噪声放大器.结果表明,在考虑了各种寄生效应的情况下,该低噪声放大器可以在0.75V的电源电压下工作,其功耗仅为2.45mW.在5.8GHz工作频率下:该放大器的噪声系数为2.9dB,正向增益S21为5.8dB,反向隔离度S12为-30dB,S11为-13.5dB.
【Abstract】 A low-voltage high isolation CMOS differential low noise amplifier(LNA)using two off-state dummy MOSFETs to neutralize the gate-to-drain capacitance(Cgd)of common source amplifier’s input stage is presented.A 5.8 GHz CMOS LNA was designed using the proposed technique in a 0.35 μm standard CMOS process.Results show that the designed LNA could be operated at supply voltage lower than 0.75 V and power consumption of 2.54 mW.At the designed frequency,the LNA achieved a forward gain S21 of 5.8 dB and 2.9 dB noise figure,the reverse isolation S12 is-30 dB,the input reflection coefficients S11 is-13.5 dB.
【Key words】 RF integrate circuits(RFIC); neutralization technique; low power; low noise amplifier(LNA);
- 【文献出处】 电子器件 ,Chinese Journal of Electron Devices , 编辑部邮箱 ,2007年02期
- 【分类号】TN722.3
- 【被引频次】1
- 【下载频次】184