【摘要】 介绍了可用于SDHSTM-64光纤传输系统的4:1复接器.整个电路采用树型结构,低速的复接单元采用动态双相伪NMOS逻辑实现,高速的复接单元采用SCL逻辑实现,提出了一种新型采用正反馈对的单端转双端电路,实现由低速单元到高速单元的逻辑变换.基于此结构的全定制单片集成电路采用0.18μmCMOS工艺设计并实现.测试结果表明,在供电电压1.8V,50Ω负载条件下,复接输出数据速率超过10Gbit/s,在标准速率10Gbit/s,输出电压峰-峰值180mV时,功耗仅为180mW,抖动4.9/s(rms),芯片面积为0.89mm2×0.7mm2.更多还原

【Abstract】 This paper describes a 4:1 multiplexer for SDH STM-64 optical communication system. The chip is constructed in tree form. A dual-phase dynamic-pseudo NMOS logic is proposed for low speed multiplexer while SCL logic for high speed multiplexer . It has been developed using 0.18 μm CMOS technology and measured on wafer. Under a 1.8 V supply , the power dissipation is only 180 mW. The measured output voltage is 180 mV based on 50 Ω load , and the jitter is 4.9/s(rms) at the 10 Gbit/s standard bit rate. The chip is 0.89 mm~2×0.7 mm~2 and the highest speed of output data is over 10 Gbit/s.更多还原