【摘要】 介绍了单电源12位A/D转换器,AD7892SQ的工作原理和CPLD(复杂可编程逻辑器件)的软核。重点说明了Verilog HDL控制程序FSM(有限状态机)和FIFO(先入先出)的设计,FSM和FIFO程序通过仿真得到了它们的仿真波形。系统通过CPLD接口提高了数据采集的实时性,而且用高级语言Verilog HDL进行设计电路,使电路设计的通用性和可移植性得到了较大的提高。更多还原

【Abstract】 This paper introduces the working principle of AD7892SQ and the software core of CPLD.The paper mainly introduces the control program design of Verilog HDLstate machine FSM and FIFO(First-in First-out).By emulating the FSM and FIFO program,the emulator waves are achieved.By using the CPLD interface the response speed of data acquisition system is improved.Moreover,the versatility and transplantation of the circuit designed by using the advanced language Verilog HDL are improved greatly.更多还原