【摘要】 为降低在定时同步算法实现时,截位对性能的影响与定时同步算法实现的复杂度,对定时同步实现时的内部子模块进行了讨论,对通过现场可编程门阵列(FPGA)实现定时同步算法的复杂度,按照单位时间内乘、加次数的方法进行了分析,并对多个定时同步模块间的关系进行了研究,提出了一种OFDM系统定时同步实现的自适应多点截位方法与2种MIMO-OFDM系统定时同步算法的简化实现方案,对实现方法在Xilinx公司的VirtexII Pro系列FPGA中的资源使用情况进行了统计,并在B3G TDD试验验证平台上进行了验证．验证结果表明,该实现方案可用于B3G TDD MIMO-OFDM系统定时同步算法的硬件实现．更多还原

【Abstract】 To reduce performance degradation by fixed-point and make the timing synchronization algorithm in MIMO-OFDM system less complicated during FPGA implementation, sub-modules in individual timing synchronizing module were discussed, and the complexity of timing synchronization algorithm implementation with field programmable gate array (FPGA) was analyzed according to multiplying and adding times in unit time, and the relationship among multiple timing synchronizing modules was studied. An automatic bit-cutting method and two simplified implementation schemes for MIMO-OFDM system timing synchronization algorithm were brought forward. Statistics on resource occupation of such schemes in VirtexII-Pro series FPGA of Xilinx Company was given, while the schemes were verified on B3G TDD system hardware platform. The results shows that the simplified implementation schemes are applicable to hardware implementation of B3G TDD MIMO-OFDM system timing synchronization algorithm.更多还原