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CMOS低功耗窄带低噪声放大器优化设计
CMOS Narrow-Band LNA Design Optimization with Low-Power Dissipation
【摘要】 阐述了一个采用Chartered 0.35μm CMOS工艺实现的应用于315 MHz幅度键控接收芯片的低功耗窄带低噪声放大器。该电路主要采用限定功耗下同时优化噪声性能和输入匹配的技术进行设计,并且采取了其他一些措施来进一步改善电路的性能。采用一个并-串谐振网络,提供镜像抑制。实验测试表明,该低噪声放大器的噪声系数为1.47 dB,功率增益为19.97 dB,输入三阶截断点为-15.53 dBm,镜像抑制为42.4 dB,功耗为1.4 mW。
【Abstract】 A narrow band low noise amplifier with low power dissipation was presented,which was implemented using the Chartered 0.35 μm CMOS technology and adopted by 315 MHz ASK receiver.The proposed circuit was designed mainly using power-constrained simultaneous noise and input matching technique,and some other measures were taken to improve the circuit performances.A shunt-series resonance circuit was used to supply image rejection.Test results show the noise figure is 1.47 dB,power gain 19.97 dB,power dissipation 1.4 mW,image-rejection 42.4 dB and input-refered third-order intercept point -15.53 dBm.
【Key words】 noise; impedance matching; power gain; linearity; image rejection;
- 【文献出处】 半导体技术 ,Semiconductor Technology , 编辑部邮箱 ,2007年05期
- 【分类号】TN722.3
- 【被引频次】5
- 【下载频次】266