【摘要】 提出了一种基于SoC平台的H.264/MPEG-4 AVC解码器设计方案,该方案基于Gaisler Re-search开发的LEON3 R ISC核,采用双总线的流水线结构,具有很高的性价比,通过在Modelsim 6.0下的仿真结果表明,硬件解码部分在200 MHz系统时钟时可以实时解码H.264 H igh 4∶4∶4 profile 4.0 level码流。更多还原

【Abstract】 In this paper,a H.264/MPEG-4 AVC decoder architecture is introduced.The decoder is based on LEON3 RISC core developed by Gaisler Research and adopts dual-bus pipeline architecture to decrease price-performance ratio.The simulation results in Modelsim 6.0 environment indicate that the hardware decoding module can decode bitstream in accord with H.264 Recommendation High 4∶4∶4 profile 4.0 level in real time when system clock frequency is 200 MHz.更多还原