【摘要】 介绍了AES算法的计数器工作模式及计算步骤;通过分析传统AES算法硬件实现的缺点,提出了一种能充分利用流水线、更高效及更适合于高速网络中使用的AES算法FPGA实现思路;并给出了综合结果以及与传统实现方法综合结果的进行了比较。更多还原

【Abstract】 This paper introduces the counter mode and its calculation step of AES algorithm: According to analyzing the disadvantage of transitional hardware implement of AES algorithm, we bring forward a new method of FPGA implement of AES algorithm which are more efficiency and more suitable for highspeed network. Finally,we give a synthesis result and the comparing between our method and the traditional method.更多还原