【摘要】 随着微电子技术的进步,集成电路的特征尺寸逐步缩小,IC设计已经向着深亚微米甚至超深亚微米设计发展,一系列由于互连线引起的信号完整性问题需要设计者更多的考虑,互连线串扰已经成为影响IC设计成功与否的一个重要因素。针对串扰这一问题本文讨论了串扰对于电路的影响,分析了深亚微米集成电路设计中对两相邻耦合RC互连串扰的成因,介绍了互连线R,C参数的提取。以反相器驱动源和容性负载为例,建立了两相邻等长平行互连线的10阶互连模型,并且针对该模型,利用Cadence软件进行仿真,分析了引起串扰的因素。在此基础上,最后给出了有效抑制串扰的方法。更多还原

【Abstract】 As development of microelectronic technique,the technology scale is under reducing,IC design has been confronted with the challenge of submicron designs.A series of SI problem should be considered by the designer,the interconnect crosstalk becomes a critical issue to the design.To this question,the paper discusses the harm of crosstalk,analyzes the causes of crosstalk between two neighboring coupled RC interconnects in submicron integrated circuit,and introduces how to get the R and C parameters.Then,sets up the tenth order model of two neighboring parallel long interconnections,and analyzes the factors of cause crosstalk by simulation using the software of Cadence.Based on the simulation get the conclusions of the effective methods to controlling crosstalk.更多还原