【摘要】 设计了一种新颖的32×32位高速流水线乘法器结构.该结构所采用的新型Radix-16 Booth算法吸取了冗余Booth编码与改进Booth编码的优点,能简单、快速地产生复杂倍数.设计完成的乘法器只产生9个部分积,有效降低了部分积压缩阵列的规模与延时.通过对5级流水线关键路径中压缩阵列和64位超前进位(CLA)加法器的优化设计,减少了乘法器的延时和面积.经现场可编程逻辑器件仿真验证表明,与采用Radix-8 Booth算法的乘法器相比,该乘法器速度提高了11%,硬件资源减少了3%.更多还原

【Abstract】 A novel 32×32-b high-speed pipeline multiplier structure is designed.Taking advantages of the merits of redundant Booth encoding and modified Booth encoding,the novel Radix16 Booth algorithm of the structure can simply and quickly generate complicated multiples.The designed multiplier has only 9 partial products,which effectively reduces the size and delay of compression array.By optimizing the compression array and the 64-b CLA(carry-lookahead) adder in the critical path of pipeline,this multiplier can effectively reduce the delay and area,too.The field programmable gate array(FPGA) simulation shows that compared to the multiplier with Radix8 Booth algorithm,the speed of this multiplier is increased by 11% and its hardware resource is reduced by 3%.更多还原