【摘要】 为了提高乘法器的综合性能,提出了一种新的冗余Booth三阶算法和跳跃式Wallace树结构,前者可以减少部分积的数目,提高部分积的产生速度,后者可以加快部分积的压缩,减少电路内部的伪翻转,从而降低功耗.基于冗余Booth三阶算法和跳跃式Wallace树结构,采用0.25μmCMOS工艺,实现了54×54位全定制乘法器,其乘法延时为4.3 ns,芯片面积为1.38 mm2,50MHz频率下的动态功耗仅为47.2 mW.模拟验证表明,与采用传统Wallace树结构和改进Booth二阶算法的乘法器相比,该乘法器的乘法延时减少了23%,功耗降低了17%,面积减少了20%.更多还原

【Abstract】 A new redundant Booth algorithm for radix8 and a novel leapfrog Wallace tree structure are presented for enhancing comprehensive performance of multiplier.The former reduces the number of partial product and enhances the generating speed of partial product;the latter has a regular layout because of the simplicity of the necessary interconnections between the compressors,and it reduces the spurious switching in the circuit to save power dissipation.By using these new techniques,a 54×54 bit multiplier is designed using 0.25 μm CMOS technology.The multiplication time is 4.3 ns at 2.5 V power supply,the active area is 1.38 mm~2,and the power dissipation is only 47.2 mW for operating frequency 50 MHz.Compared to the conventional multiplier with modified Booth algorithm for radix-4 and Wallace tree architecture,the proposed techniques employed in the multiplier reduces 17% of the power dissipation and 23% of the multiplication time,and the area of multiplier is reduced by 20%.更多还原