【摘要】 基于逻辑努力(LogicEffort)分析优化了CMOS串行传输链延迟时间,给出了HSPICE模拟结果。结果表明:当逻辑链中每一级逻辑门具有相同的gihi,可以减小链的延迟时间,并且链中逻辑门的个数N≈lnFln(0.71p+2.82)时,通过逻辑链的总延迟可以进一步减小。更多还原

【Abstract】 Time delay of CMOS serial transmission chain is optimized and analyzed based on Logic Effort,and HSPICE simulation results are preseted.The study has come to the following:When each logic gate in the CMOS serial transmission chain has the same gihi,it can reduce the delay time of the chain;when the number of the logic gate in the chain N≈lnF ln(0.71p+2.82),the dalay time of the chain can be reduced more.更多还原