【摘要】 提出了一种基于提升算法的二维离散5/3小波变换(DWT)高效并行VLSI结构设计方法。该方法使得行和列滤波器同时进行滤波,采用流水线设计方法处理,在保证同样的精度下,大大减少了运算量,提高了变换速度,节约了硬件资源。该方法已通过了VerilogHDL行为级仿真验证,可作为单独的IP核应用在JPEG2000图像编、解码芯片中。该结构可推广到9/7小波提升结构。更多还原

【Abstract】 A parallel pipelined architecture that performs the forward and inverse 5/3 discrete wavelet transform (DWT) is proposed by using a lifting-based scheme. The architecture uses the row and column filters for filtering simultaneously. The whole architecture is optimized in the pipeline design way to increase the transform speed, and achieve higher hardware utilization. Finally, the architecture has been implemented in behavioral Verilog HDL. The architecture can be used as a compact and independent IP core for JPEG2000 VLSI implementation and various real-time image/video applications,and can be applied to 9/7 discrete wavelet transform.更多还原