【摘要】 在数字系统设计中,提高系统的运行速度是设计的一个难点．本文根据流水线设计的基本思想,介绍了利用VHDL语言描述流水线模块的方法,并以4位整数乘法器的设计为例阐述流水线技术设计的过程．通过流水线设计的不同乘法器在MAXPLUSII中编译、综合下载到FPGA中后,对其特性进行统计分析,证明了流水线技术在提高运算速度方面的明显作用．更多还原

【Abstract】 In the design of digital system,improving speed of the system is one difficulty.According to the basic theory of pipeline technology,the method that using VHDL language describes pipeline module and the process of design of the 4 bits pipeline integer multiplier is introduced.The effect of the pipeline on the improving speed is proved by designing different pipeline integer multiplier by compile and synthesis and loading to FPGA in MAXPLUSII.更多还原