节点文献
数字电路的高层测试技术及其发展
High-Level Testing of Digital VLSI Circuits and Its Developing Trend
【摘要】 简要介绍了数字VLSI电路高层测试的概念,主要的高层测试方法,高层测试中所采用的故障模型及其与门级stuck-at故障的对应关系;并展望了高层测试技术的发展趋势。
【Abstract】 High-level testing of digital VLSI circuits is briefly reviewed.The most important high-level test approaches are described.High-level fault models and its mapping with the stuck-at faults are presented.And finally,the developing trend of high-level testing is discussed.
【关键词】 数字电路;
VLSI;
高层测试;
故障模型;
可测性设计;
测试综合;
【Key words】 Digital IC; VLSI; High-level test; Fault model; Design for testability (DFT); Test synthesis;
【Key words】 Digital IC; VLSI; High-level test; Fault model; Design for testability (DFT); Test synthesis;
【基金】 国家自然科学基金资助项目(90207016)
- 【文献出处】 微电子学 ,Microelectronics , 编辑部邮箱 ,2006年02期
- 【分类号】TN79
- 【被引频次】4
- 【下载频次】212