【摘要】 提出一种适于RTL综合的VLSI架构,3个链表由片上RAM实现,同时建立输入数据和初始化链表并行执行的模式·给出3个链表扫描和幅度细化的控制器及相应的有限状态机,并对其操作流程进行形式化的描述·最后对三维多分等级树的硬件模型进行了综合与仿真·仿真实验证明,该设计方法正确有效,在FPGA上工作频率达58MHz,满足视频编码器的实时性要求·更多还原

【Abstract】 A VLSI architecture for RTL synthesis is proposed, which needs three RAMs to construct the three lists. It builds up the parallel execution mode of input data and initializing lists simultaneously. A controller for the three list scanning and refining, and its finite state machine are also given. The operation flow is given by formal description. Finally, the hardware model of three dimensional set partitioning in hierarchical trees (3D SPIHT) is synthesized and simulated. Experimental results show that the design method is correct and effective. It can work with 59MHz frequency on FPGA and meets the real time needs of video encoder.更多还原