【摘要】 设计并实现了一个片上可编程系统(SOPC)设计工具ESIGE,它通过开放式的结构对不同来源的异构软核IP进行封装,对SOPC设计人员屏蔽了IP的复杂性·不同实现方式和不同总线接口的IP可以混合使用·ESIGE通过层次化的集成和灵活的IP互连方式支持复杂的IP互连结构,利用虚拟设计和自动化的IP集成显著地降低了SOPC设计的工作量·更多还原

【Abstract】 A system on a programmable chip (SOPC) design tool called ESIGE is presented. It provides an open structure that encapsulates heterogeneous soft IP cores from different providers, and hides the complexity of IP cores from the SOPC designers. IP cores with different implementation techniques and different bus interfaces can be integrated together. ESIGE integrates IP cores in a hierarchical and flexible way, supports complex integration structure. With virtual design and automatic IP integration, ESIGE reduces the complexity of SOPC design significantly.更多还原