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多级滤波算法的ASIC实现

ASIC implementation for multilevel filter algorithm

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【作者】 陈朝阳孙剑伟郑兆青张天序

【Author】 Chen Chaoyang Sun Jianwei Zheng Zhaoqing Zhang TianxuAssoc.Prof.;Institute for Pattern Recognition & AI,Huazhong Univ.of Sci.& Tech.,Wuhan 430074,China.

【机构】 华中科技大学图像识别与人工智能研究所华中科技大学图像识别与人工智能研究所 湖北武汉430074湖北武汉430074

【摘要】 提出红外图像小目标检测多级滤波算法的一种ASIC体系结构实现方案.该结构有三个数据通道,分别级连不同数量的1×3基本滤波模板;每路数据通道采用流水线结构,其中乘法电路由移位相加电路构成以提高运算速度;采用定点运算,计算精度为8位二进制小数,可处理位宽为8~16位的数据,吞吐量5 M pixel/s~10 M pixel/s,支持128×128,256×256,320×240三种帧格式的图像滤波.设计采用SMIC 0.35μm工艺,芯片面积为3.2 mm×2.7 mm,芯片内部工作频率为50 MHz.芯片滤波实现方式相对软件实现的方式,最大绝对误差0.483 3,可满足实际精度的要求.该芯片可以用于同时检测大小不同小红外小目标.

【Abstract】 An ASIC architecture was proposed on the basis of the multilevel filter algorithm for detecting the small targets of infrared images.This architecture possessed three data-paths and cascaded different basic 1x3 filter templates respectively.Pipeline technique was used in each data-path.In order to improve the process speed,the multipliers in the data-path were substituted by shift-and-add circuits.Fixed point calculation was implemented with the precision of 8bits.This architecture can process data with 8-16 bits.Its throughput capacity is 5Mpixel/s~10Mpixel/s.It support image sizes with 128×128,256×256 and 320×240.SMIC 0.35μm technology was adopted for this design.Chip area was 3.2mm×2.7mm and inner frequency was 50MHz.The maximum absolute error was 0.4833 between chip implementation and software implementation,meeting the practical requirements.The chip can be used to detect infrared small targets with different sizes simultaneously.

【基金】 国家重大基础预研项目(413010701-3);国家自然科学基金重点资助项目(60135020)
  • 【文献出处】 华中科技大学学报(自然科学版) ,Journal of Huazhong University of Science and Technology(Nature Science Edition) , 编辑部邮箱 ,2006年02期
  • 【分类号】TP274.52
  • 【被引频次】6
  • 【下载频次】149
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