【摘要】 采用FPGA实现FIR数字滤波器硬件电路的方案,基于只读存储器ROM查找表的并行分布式算法,设计文件采用Verilog HDL语言进行描述。该设计方案在MAX+PlusII上进行了实验仿真和时序分析。结果表明:它克服已有软件和硬件难以达到的对信号处理缺陷,既具有实时性,又兼顾了一定的灵活性,完全可以达到实际应用的要求。另外,对优化硬件资源利用率、提高运算速度等工程实际问题也进行了探讨。更多还原

【Abstract】 This paper discusses a method to design the FIR filter on FPGA,on the basis of parallel-distributed arithmetic method,using ROM based LUT.The designing file of FIR digital filter is described with Verilog HDL and passes the experimental simulation and timing analysis in MAX+PlusII.The result of simulation proves that this method is feasible,efficient,and is capable of overcoming the disadvantage of software and hardware techniques available for implementation which suffers from the failure to meet the demand for a real-time and flexible requirement for signal processing in the same time.The method not only fulfils the real-time requirement,but also shows greater flexibility.The paper studies some practical problems as to how to optimize the utilization per cent of the hardware and improve to the computed speed.更多还原