【摘要】 FIR滤波器是一种被广泛应用的基本的数字信号处理部件。现提出采用MATLAB的窗函数方法设计并在FPGA上实现高速FIR滤波器的一种新的方案。这种结构采用流水线技术,通过对高速乘法器的合理分割并组合Wallace加法树阵列构成,可以方便地调整滤波器的阶数和系数,适合不同场合的应用。通过编程调试结果表明,该设计是可靠的,可作为高速数字滤波器设计的较好方案。更多还原

【Abstract】 FIR filter is a basic processing unit for digital signal in common use.This paper presents a scheme which is designed with a FIR filter of high linear phase and can effectively realized in FPGA.This structure is made into effect by a rational division of the high-speed multiplier and recoganization in Wallace adder array tree with the aide of pipelining technology.The orders and the coefficients of the filter may flexibly be tuned,and it may suit to versatile applications.It is a better scheme for designing high speed digital filter through the programming and debugging.更多还原