【摘要】 提出了一种应用于基于Lifting的二维离散小波变换(2D-DWT)硬件设计的算法,即减少规整化乘.该算法能够大大减少2D-DWT处理过程中的乘法运算次数,降低系统功耗.给出了应用该算法的新型9/7小波结构,该结构通过适当的配置可以既作为正向变换滤波器又作为反向变换滤波器,既能实现5/3小波又能实现9/7小波.对该结构使用Verilog HDL语言进行RTL级描述,在SMIC 0.18μm工艺下综合得到最高工作频率为150MHz,等效门数是15 500.更多还原

【Abstract】 A reduced scaling multiplications(RSCM) algorithm is proposed for the 2 dimensional discrete wavelet transform(2D-DWT).This algorithm reduces the number of multiplication operations and the system power as well.A novel(9/7) architecture was given which could be used as FDWT or IDWT and either 9/7 filter or 5/3 filter could be realized.The architecture is described in RTL-level Verilog.The estimated number of gates of the proposed architecture in SMIC 0.18 μm technology is 15 500,while the estimated frequency of operation is 150 MHz.更多还原