节点文献
基于切割法的时序电路等价验证
Sequential Equivalence Check Using Cuts
【摘要】 在Van Eijk时序电路等价验证算法中引入切割法,提出一种改进算法.由切割法引发的错反问题同时得到解决,合理的切割可以使时序电路等价验证只需较少时间.改进算法用SAT解答器作为计算引擎.实验结果表明,改进算法的运行速度约为原先算法的2倍.
【Abstract】 An improved algorithm which combines cut points technique with Van Eijk’s sequential equivalence checking algorithm is presented.The false negative problem caused by the cut technique is solved,and reasonable cut results in less time for sequential equivalence checking.The calculating engine of the proposed algorithm is SAT-Solver.Experimental results show that the proposed algorithm can double the original speed.
【关键词】 半导体技术;
计算机辅助设计;
形式验证;
SAT解答器;
【Key words】 semiconductor technology; computer-aided design; formal verification; SAT-solver;
【Key words】 semiconductor technology; computer-aided design; formal verification; SAT-solver;
【基金】 国家自然科学基金资助项目(90207002);国家“八六三”计划资助项目(2002AA1Z1460)
- 【文献出处】 复旦学报(自然科学版) ,Journal of Fudan University(Natural Science) , 编辑部邮箱 ,2006年01期
- 【分类号】TN79
- 【被引频次】4
- 【下载频次】53