【摘要】 优化顶层互连线性能已成为超深亚微米片上系统(SOC)设计的关键.本文提出了适用于多个工艺节点的串扰约束下顶层互连线性能的优化方法.该方法由基于分布RLC连线模型的延迟串扰解析公式所推得.通过HSPICE仿真验证,对当前主流工艺(90nm),此优化方法可令与芯片边长等长的顶层互连线(23.9mm)的延时减小到182ps,数据总线带宽达到1.43 GHz/μm,近邻连线峰值串扰电压控制在0.096Vdd左右.通过由本方法所确定的各工艺节点下的截面参数和性能指标,可合理预测未来超深亚微米工艺条件下顶层互连线优化设计的发展趋势.更多还原

【Abstract】 It’s crucial to optimize global interconnect performance in ultra deep sub-micron System-On-a-Chip designs.In this paper,the optimized method to improve delay-bandwidth performance under crosstalk constraint,suitable to various technology nodes,is proposed from analytical formula based on distributed RLC model.It’s verified through HSPICE simulation that,by utilizing this method,the optimization of edge-length global interconnect of mainstream 90 nm technology can achieve delay of 182 ps,data bandwidth of 1.43GHz/μm,and near line peak crosstalk voltage within 0.096V_dd.Through cross-section parameters and performance targets determined by this method under various technology nodes,the trend of global interconnect design is reasonably predicted along with continuously scaling down of semiconductor devices.更多还原