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深亚微米下芯片电源网络的设计和验证

Design and Validate the Chip’s Power-Network in DSM

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【作者】 樊俊峰王国雄沈海斌楼久怀

【Author】 FAN Jun-feng,WANG Guo-xiong,SHEN Hai-bin,LOU Jiu-huai Institute of VLSI Design,Zhejiang University,Hangzhou 310027,China;College of Info Science and Engineering,Zhejiang University,Hangzhou 310027,China

【机构】 浙江大学超大规模集成电路设计研究所浙江大学超大规模集成电路设计研究所 杭州310027杭州310027

【摘要】 随着芯片集成度的逐渐提高,芯片单位面积所消耗的功耗也越来越大,因此,可靠的电源网络设计和验证已成为芯片设计成败的关键因素之一。在以往,集成电路(IC)设计工程师往往根据经验来设计电源网络,但工艺到0.18μm,这往往会引起芯片功能失效。根据这个问题,本文首先介绍电压降(IR-Drop)和电子迁移率(Electro-migration)现象和对芯片性能的影响;其次,提出一种有效的电源网络设计和验证方法,并在芯片的物理设计初期对电源网络作可靠性估计;最后,经过椭圆曲线加密芯片(ECC&RSA)的流片,表明采用该方法设计的芯片,工作情况良好。

【Abstract】 With the development of IC manufacture,more and more transistors can be integrated into one chip,so the consumption of power per area becomes bigger and bigger.So the reliability of power-network becomes the more important factor in IC design.Before,the IC designer only based on their experience to design power-network,but when the process is under 0.18 μm,this always causes the failure of chip’s function.According to this problem,this paper discussed the reasons and the influences of IR-drop and EM(Electro-migration) and introduced a new method of designing and validating power-network.The power-network in the beginning of designing chip was designed and validated is physics.Finally,this method has been used in actual design,which shows its efficiency.

【关键词】 电源网络电压降电子迁移率
【Key words】 power-networkIR-dropEM(Electro-migration)
  • 【文献出处】 电子器件 ,Chinese Journal of Electron Devices , 编辑部邮箱 ,2006年04期
  • 【分类号】TN47
  • 【被引频次】10
  • 【下载频次】155
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