【摘要】 在分析影响锁相环性能的各种因素的基础上,采用相应的优化方法设计了一款全集成的1.2GHzLC锁相环。详细介绍了该锁相环中各模块电路(包括LC型压控振荡器,预分频器,分频器,鉴频/鉴相器,含有带隙基准电流源的电荷泵以及片上无源滤波器等)的设计,并且给出了仿真结果。该锁相环采用SMIC0.18μmRFCMOS工艺设计实现,其中无源滤波器也集成在片上,实现了完全片上集成。更多还原

【Abstract】 On the base of analyzing the factors affecting the per formance of the PLL, the corresponding scheme for optimization is presented and a 1.2 GHz LC phase-locked loop (PLL) is designed. The circuit design of the PLL that consists of a LC-tank circuit, prescaler, frequency divider, phase/freque ncy detector, charge pump that includes a bandgap current reference and a passiv e loop filter is introduced and the simulation results are given. The PLL is des igned in SMIC 0.18 μm 3.3 V 1P6M CMOS RF technology and the passive loop filter is also on-chip and no off-chip components are needed.更多还原