【摘要】 为了减小流水线结构A/D转换器的量化误差,提出了一种简单有效的改进算法。该算法在不附加任何额外电路的情况下,通过对模拟量化比较电平的调整,实现了舍入式流水线结构,其量化误差范围在-1/2LSB与1/2LSB之间。提出了改进算法的简化结构,并作了分析。利用MATLAB完成了算法仿真,证明该算法满足舍入式的要求,且适用于任何位数的流水线结构。更多还原

【Abstract】 In order to reduce the quantization error of pipelined A/D converter, a simple and efficient modified algorithm is presented. Without any other additional circuit, the algorithm achieved a pipelined architecture of rounding method by adjusting the quantization level, the quantization error ranged from -1/2LSB to 1/2LSB. The method was simulated by MATLAB, showing the algorithm met the requirement of rounding method and applied to the pipelined architecture of various bits.更多还原