【摘要】 介绍了一种采用新型结构的应用于DSP处理器的多功能高速低功耗乘累加单元(MAC)。该设计采用了异步互锁流水线技术,极大的降低了功耗。在整个设计的关键路径即部分积产生和生成部分采用的互补部分积字校正(CPPWC)和三维压缩法(TDM)很好的优化了设计,提高了速度。嵌入该乘累加单元的DSP处理器采用SMIC0.18CMOS工艺进行了流片。经测试,该设计优于采用传统结构的同类设计,其时延为3.34ns,功耗为13.9247mW。更多还原

【Abstract】 The extreme power reduction derives from the asynchronous interlocked pipeline technique MAC adopts. And the speed is greatly increased by introducing the complemented partial product word correction (CPPWC) algorithm and three dimensional reduction method (TDM) in the partial product generation and reduction path. The DSP processor embedded with MAC has been implemented in SMIC 0.18 CMOS technology. And MAC shows low power dissipation and high speed than related design using conventional architecture. The delay and power consumption of MAC are 3.34 ns and 13.924 7 mW respectively.更多还原