【摘要】 本文提出了一种高性能有限脉冲响应(FIR)滤波器结构,用于视频格式转换芯片中尺寸缩放模块算法的实现,该结构采用流水线技术1,同时结合了并行性、系数对称性、“0”的特性和乘法优化(加法代替);阐述了该FIR滤波器的设计原则和优化方法,给出了该FIR滤波器FPGA实现的框图和综合结果,与传统结构实现的FIR滤波器比较具有更高的性能和兼容性。更多还原

【Abstract】 In order to realize one specific scaling algorithm used by a real-time video processor, a new high-performance FIR filter structure which utilizes several distinct means of optimization, such as high-parallelization, parameter symmetry, ‘zero’ data characteristic and reduced multiplier (replaced by adders) is developed. The design principle and means of optimization are discussed in detail, then the FPGA implementation block diagram and synthesis result of this FIR filter are shown. A comparison between traditional filters and this new FIR filter is listed to prove high performance and compatibility of the proposed approach.更多还原