【摘要】 通过研究几种高速Viterbi译码器的ACS(加比选)单元的结构,提出一种ACS单元新的设计方法。设计中采用Radix-4网格结构,能提高译码器的吞吐量;而简单的逻辑可以有效降低译码器的资源占用率。更多还原

【Abstract】 By studying several structures of the ACS(Add-Compare-Select)Unit, this paper proposes a new method to design ACS Unit. The throughput could be improved by adopting Radix-4 net, and consumption resource could also be reduced due to simple logic structure.更多还原