【摘要】 本文提出了一种新型的适用于USB2.0高速模式480MHz时钟产生的单片锁相环(PLL)电路。该PLL电路由一个鉴频鉴相器电路、一个电荷泵、一个低通滤波器、一个压控振荡器和分频器组成。论文着重对由环型差分对组成的压控振荡器电路进行了优化。电路的设计基于TSMC的0.25μmCMOS混合信号模型,电路的前后仿真结果表明该电路不仅能产生频率为480MHz的时钟信号,并且抖动(jitter)只有2psrms,锁定时间(locktime)是1.8μs,完全满足USB2.0接口芯片对PLL的要求。更多还原

【Abstract】 A monolithic Phase-Locked Loop (PLL) used for high-speed serial link is presented. The PLL includes a phase frequency detector, a charge pump, a low pass filter, a voltage controlled oscillator and a frequency divider .We emphasized the optimization of the voltage controlled oscillator (VCO) consisted of differential inverter ring. The design of PLL chip is based on 0.25μm CMOS mixed-signal model of TSMC. The pre and post-simulation results of the circuit indicate that the circuit produces 480MHz frequency clock with a low jitter of only 2ps rms and the lock time of 1.8us.It meets the need of USB2.0 interface circuit entirely.更多还原