【摘要】 设计实现了一种IDEA算法(International Data Encryption Algorithm)加/解密模块。根据IDEA算法的基本原理设计了IDEA密码芯片,并采用了4级流水线结构。对主要影响算法实现效率的模乘运算转换为部分积模加运算。仿真和综合结果表明该模块在17.14MHz的时钟频率下可达到96Mb/sec的加/解密速率。更多还原

【Abstract】 An FPGA implementation of the international data encryption algorithm (IDEA) is presented.Based on the analysis of the IDEA algorithm an IDEA chip and pipelined IDEA function into four-pipelined one is designed.The simulation and synthesis show that the design has 96 Mb/sec encryption/decryption rate under the 17.14 MHZ system clock rate.更多还原