【摘要】 采用TSMC公司的标准0·25μmCMOS工艺,设计并实现了一个全集成的1·244GHz低功耗锁相环,提出了一种锁相环相位噪声的行为级模拟方法.锁相环的核心功耗仅为12mW,输出时钟信号均方抖动为6·1ps,单边带相位噪声在10kHz频偏处为-106dBc/Hz.更多还原

【Abstract】 A low-power phase-locked loop (PLL) is designed and fabricated in TSMC’s standard 0.25μm CMOS process.A behavioral simulation method for the PLL’s phase noise is presented.The power consumption of the PLL core is about 12mW.The rms jitter is 6.1ps,and the SSB phase noise is -106dBc/Hz at a 10kHz offset.更多还原