【摘要】 提出了一种适用于分数分频锁相环频率综合器的全数字噪声整型ΔΣ调制器电路结构新的设计方法,并将其最终实现.采用了流水线技术和新的CST算法优化多位输入加法器结构,从而降低了整体的复杂度和功耗.这种电路结构通过了Matlab的行为级仿真,ASIC全定制实现并流片,该结构也通过VHDL综合实现验证,最后给出的测试结果表明该电路具有良好的性能,可应用于单片千兆赫兹级低功耗CMOS频率综合器中.更多还原

【Abstract】 This paper presents the design considerations and implementation of a novel topology digital multi-stage-noise-shaping (MASH) delta-sigma modulator suitable for fractional-N phase-locked-loop (PLL) frequency synthesis.In an effort to reduce the complexity and dissipation,a pipeline technique has been used, and the proposed carry save tree (CST) algorithm optimizes the multi-input adder structure.The circuit has been verified through Matlab simulation,ASIC implementation,and FPGA experiment,which exhibits high performance and potential for a gigahertz range,low-power monolithic CMOS frequency synthesizer.更多还原