【摘要】 对国内外几种SIMOX硅薄膜样品进行位错密度测量 ,再用紫外光致荧光法(UVF)对其在集成电路工艺流片前后的Fe、Cu、Ni、Mo等重离子沾污作对比测定 ,结合SIMOX/MOS管的漏电特性 ,作了简要的机理分析。结果表明 ,重离子沾污不但在形成SIMOX结构时产生 ,在集成电路工艺流片过程中也会发生 ,并明显影响MOSFET的性能。重金属杂质的沾污程度与SIMOX材料的位错密度密切相关 ,位错密度可能是沾污重金属原子的吸收中心。要降低重金属杂质的沾污首先必须降低SIMOX材料的位错密度。更多还原

【Abstract】 The dislocation density of three kinds of SIMOX samples was obtained by Secco etching.The contamination of heavy metal impurity (Fe,Cu,Ni,Mo)was measured using UVF technology for these samples before and after SIOMX/CMOS processing.It’s mechanism is analyzed briefly by source?drain leakage characteristics of SIMOX/MOS device.The results show that heavy metal impurity contamination not only occurred during implantation forming SOI structure but also in the course of IC processing and had a big influence on the MOSFET property.The degree of contamination during IC processing related closely to the dislocation density of SIMOX structure.The dislocation density could be the absorption center of the atom of heavy metal impurity.To decrease the contamination of heavy metal impurity the dislocation density of SIMOX material should be decreased first.更多还原