【摘要】 给出了一种 GF( 2 56 )域上的 RS( 2 0 4 ,1 88)码编码器的实现算法 ,建立了 C语言行为级模型和 RTL级硬件模型。采用了具有对称系数的生成多项式 ,减少了有限域乘法器的个数。通过逻辑综合、优化得到了电路网表与 FPGA网表 ,并进行了二者的仿真验证。该电路的规模约为41 0 0门左右 ,约为一般的该编码器 70 %。更多还原

【Abstract】 This paper describes the arithmetic to implement RS (204,188) encoder on GF (256).A behavior model described by C language and a RTL hardware model has been established.This encoder has adopted symmetrical coefficients in order to reduce the multipliers of finite field.The circuit net and FPGA net have been achieved by logic synthesis and optimize technology.These nets are simulated and validated,furthermore.The circuit scale of encoder that has been synthesized is about 4100 gates.Its frequency is up to 35MHz,and its scale is about 70% of the ordinary encoder.更多还原