【摘要】 段高速缓存器加载是微处理器保护方式下多任务调度、虚拟段式存储器管理及指令集使用频度较高的部分。文中探讨了段高速缓存器加载的数据结构和定义 ,给出了保护方式下段高速缓存器加载算法 ,提出了用于段高速缓存器加载的保护测试单元的细胞群结构。最后 ,用 EDA工具SYNOPSYS对段高速缓存器加载算法的微程序和段高速缓存器加载的保护测试单元 RTL级的 VHDL描述进行了综合与仿真 ,验证了其设计的正确性与有效性更多还原

【Abstract】 In microprocessor protected mode, the segment register does not represent the segment base address as in real mode but becomes a selector which can index a descriptor in the GDT/LDT (Global/Local descriptor table). A descriptor contains a segment base address, a limit and an attribute. The number of visits to descriptors in memory can be reduced by having every segment register set up a corresponding segment cache to hold a descriptor. This paper firstly analyzes the definitions and data structures for segment cache loading to design an algorithm for segment cache looding. The algorithm is then used to propose a kind of cell group architecture to build the PTU (Protection Test Unit) for segment cache loading. A boolean value is generated from the PTU to control branching of the microprogram for the segment cache loading algorithms. The RTL VHDL description for the PTU and the microprogram have been synthesized for the algorithm with SYNOPSYS tools to prove the validity of the PTU.更多还原