【摘要】 锁存器与触发器的综合是 RTL综合中时序逻辑综合子系统的主要研究问题之一 ,不同的 RTL时序电路描述综合出的元件各不相同 .文中从 VHDL 语言的 RTL 描述特征入手 ,研究了 RTL 综合中锁存器与触发器的综合方法 ,阐述了采用锁存器及触发器的各种不同情况 ,同时说明如何才能正确地区分锁存器及触发器 .文章最后的实验结果验证了该方法更多还原

【Abstract】 Synthesis of latch and flip flop is one of the main problems which should be solved in sequential logic synthesis system. Different components can be inferred from different RTL circuit descriptions. This article discusses the synthesis of latches and flip flops described in RTL form with VHDL language, clarifies the different cases of using latches and flip flops in detail, and shows how to distinguish latches from flip flops correctly. Experiment result at the end of this article verifies the effectiveness of presented approach.更多还原