【摘要】 本文从开发指令级并行度ILP的角度出发,分析了超标量、超流水线处理器的体系结构特点,在此基础上给出了一个定点超标量RISC核设计。该设计采用Top-down设计方法,含三个流水执行单元,指令动态调度,实现非阻塞高速缓存non-blocking-caches机制。更多还原

【Abstract】 By exploiting instruction-level parallelism (ILP), the characteristics of architecture of super-scalar and super-pipelined processors are analyzed. Based on the achievement of research, a design of RISC core by super-scalar and super-pipelined technique is given. According to the proposed design, three pipelined execution units are configured by top-down methodology. Instruction dynamic scheduling and non-blocking-caches mechanism are also implemented.更多还原