【摘要】 在通常适合于制作埋沟 Si Ge NMOSFET的 Si/弛豫 Si Ge/应变 Si/弛豫 Si Ge缓冲层 /渐变 Ge组分层的结构上 ,制作成功了 Si Ge PMOSFET.这种 Si Ge PMOSFET将更容易与 Si Ge NMOSFET集成 ,用于实现 Si Ge CMOS.实验测得这种结构的 Si Ge PMOSFET在栅压为 3.5 V时最大饱和跨导比用作对照的 Si PMOS提高约 2倍 ,而与常规的应变 Si Ge沟道的器件相当更多还原

【Abstract】 Due to the high mobility both in the relaxed SiGe and Strained Si,a novel SiGe PMOSFET is successfully fabricated on the heterostructure Si/relaxed SiGe/Strained Si/Relaxed SiGe buffer layer/grading layer,which is commonly used in “buried” SiGe NMOSFET.It is easy to integrate the SiGe PMOSFET with SiGe NMOSFET to form SiGe CMOS.The channel of this device is in strained Si and relaxed SiGe according to different gate voltage.And the process of fabrication is also presented.The maximum saturated transconductance is found twice larger than that of the control Si PMOS,and approximates to that of the traditional strained SiGe channel PMOS.更多还原