【摘要】 以视频编码器片上系统的设计为实验对象 ,提出了一种具有较高层次的软硬件协同设计方法 .运用该方法着重对视频编码器芯片上 RISC核进行设计 ,并采用 0 .35μm CMOS工艺在 EDA工具上实现 .综合结果表明 ,在系统层次上展开系统芯片的软硬件协同设计 ,具有具体结构对算法的适应性好、设计周期短、系统易于优化等优点更多还原

【Abstract】 Taking the design of video encoder for example, this paper presents a new software/hardware co design method at high level of abstraction. We use this method to design the reduced instruction set computing (RISC) core in video encoder, and compile behavioral level Verilog hardware description language (HDL) of this RISC core with Synopsy′s Design Compiler in 0.35μm CMOS technology. The synthesis information of electronic design automation (EDA) tools about area, power, and timing shows that this method has the advantage of fitting special architecture into algorithms easily. Thus, use of this hardware/software co design method can lead to raise the potential quality and shorten the development time of electronic products.更多还原