【摘要】 从两种不同结构形式的部分耗尽器件性能研究入手，以0.6μmNMOS工艺为基础，设计并研制了在芯片内部具有高Q值的平面电感的SOI低噪声放大器电路。电路在1.5V电压下,中心频率1.8GHz时峰值增益为24dB，浮体SOI器件结构的LNA电路比体接触结构的LNA电路有更高的增益和较低的噪声。更多还原

【Abstract】 From two kind of the partially － depleted (PD) SOI devices characteristics, an LAN circuits with high Q － factor planar inductor has been successfully designed and fabricated by using 0.6 μ m NMOS PD/SOI technology. 24 dB peak gains are obtained at 1.5V and 1.8 GHz. The comparison between circuits with FB and BC devices shows that the former has better performance for RF applications.更多还原