【摘要】 高速芯片设计中所有时序的容差都非常小，而互连延迟在整个时序预算中所占的比例随着速度的升高而变大。因此为了满足其高速性能，一方面要精确地定位电路各部分的延迟模型，另一方面必须把实际布图后互连延迟信息返标 到逻辑综合环境。文章结合ＢＡＰ１０２４ 芯片的设计，对这方面进行了研究更多还原

【Abstract】 The tolerance error of timing is very small in high speed chip design The quality of designs produced by design compiler depends on the accuracy of its wire estimation since the role of interconnect in determining the performance of high speed systems has been steadily increasing It is a need for more accurate and elaborate delay models, for the more accurate floorplan wiring estimates being back annotated in projecting the high speed chip This paper makes some investigations of these respects combining the design of BAP1024(Bit serial Array Process with 1024 process elements) chip更多还原