【摘要】 介绍了一种适用于数字视频处理中垂直滤波的嵌入式ＦＩＦＯ的结构，可同时写入并读出多行数据。电路采用了三管动态存储单元和带缓冲的Ｉ／Ｏ单元，并针对Ｙ－Ｃ分离算法的要求对控制电路进行优化。经先进半导体制造公司１．０μｍ多晶栅双层铝布线工艺流片测试，在４０ＭＨｚ时钟下工作正常。更多还原

【Abstract】 An embedded FIFO architecture for vertical filtering in digital video processing is proposed, which can write in and read out several lines of data simultaneously. Three transistor dynamic cells and buffered I/O control logic are used for the device. The control circuit is optimized for Y C separation system. Fabricated with ASMC 1.0 μm , poly gate, double metal CMOS technology, the chip operates properly at 40 MHz.更多还原