【摘要】 讨论了一种在ＦＰＧＡ中可实现的ＦＩＲ滤波器结构。该结构采用基于流水线型的乘加器和进位保留的加法阵列。为减少硬件消耗，乘法器使用的部分积由修改的Ｂｏｏｔｈ算法产生。ＦＩＲ滤波器用ＶＨＤＬ进行描述，并综合到ＦＰＧＡ中。从综合结果来看，提出的ＦＩＲ结构可以在ＸＣ４０２５ｅ－２中以５０ＭＨｚ的时钟频率高速运行。更多还原

【Abstract】 A digital FIR filter architecture implemented in FPGA is described.The FIR architecture is based on a pipelined multiply add accumulator(MAC)which employs carry save array.To save the delay time and hardware resources,multiplier uses the partial products generated by modified Booth algorithm.The FIR architecture is written in VHDL,and is synthesized into FPGA.The synthesis result shows that the proposed FIR architecture can run at 50 MHz clock rate in FPGA XC4025e 2.更多还原