【摘要】 提出了一种适于实现数据通路(Datapath)逻辑的FPGA结构FDP。该结构的主要创新之处在于采用了两条通用反馈逻辑、基于全加器的通用逻辑单元、基于信号流的不对称连线结构和并行的测试扫描链。SPICE模拟结果表明,用0.8μm的工艺,FDP块内延时2.7ns,平均进位链延时0.1ns。工艺映射的实验结果显示,在实现数据通路中的常用电路时,新模块比基于LUT的FPGA模块平均节省70%的MOS管数更多还原

【Abstract】 A new FPGA architecture for datapath applications is presented Novel aspects of the architecture are two rows of general purpose feedback logic,full adder based logic cell,signal flow based asymmetrical interconnection resources and parallel test scan chains Results from SPICE simulation show that the in cell delay is 2 7 ns and the average carry chain delay is 0 1 ns for 0 8 μm process The technology mapping indicates that the proposed FPGA can save 70% of MOS transistors on the average,compared with LUT based FPGA′s,when used for implementing datapath circuits更多还原