【摘要】 介绍一种ＳＤＨ 系统专用集成电路的设计，它可以从ＶＣ４ 信号中任意上下分插出多达２１ 个Ｅ１ 信号，包括Ｅ１ 的线路编解码及数字解同步器、码速调整及去调整、ＶＣ１２开销的终结及生成、ＴＵ１２ 的指针调整及解释、ＶＣ４ 的合成及分解。电路设计既充分考虑ＩＴＵ－Ｔ的标准，又结合实际系统设计，克服了以前电路的缺点，具有规模大、功能完善、性能优越的特点更多还原

【Abstract】 This paper introduces the design of a Synchronous Digital Hierarchy(SDH) Application Special Integrated Circuit(ASIC). The chip can demultiplex and muiltiplex up to 21 E1 signals form and to VC4 frame including codec of E1 line signal, digital desynchronizer, bit rate justification, TU12 pointer interpretation and generation, VC12 overhead termination and generation. The design of the chip not only accords with the ITU T recommendiations but also considers the system application. It has the characters of large scale, comprehensive functions and perfect performances.更多还原