【作者】 韩蔚峰； 陈鹏； 曹振新；

【Author】 Weifeng Han;Peng Chen;Zhenxin Cao;Southeast university;

【机构】 东南大学；

【摘要】 北斗导航信号到达用户接收机时相当微弱,极易受到有意或无意的干扰,恶化定位误差。以功率倒置(Power Inversion,PI)算法为代表的盲干扰消除技术通过优化设计天线阵权值,可以在未知干扰先验信息的条件下实现对干扰的有效抑制,提升系统的输出信干噪比(SignaltoInterferenceplus Noise Ratio, SINR)。以抗干扰性能和实现复杂度为目标,提出了基于System Generator的PI算法实现结构,高效进行数字系统的开发,并探索现场可编程门阵列(Field Programmable Gate Array, FPGA)的并行处理性能,通过基于最小均方误差(Minimum Mean Square Error, MMSE)准则的直接求逆算法、最陡下降算法、以及共轭梯度(Conjugate Gradient, CG)算法,实现了PI算法的FPGA北斗导航抗干扰系统。通过仿真阵元间距为半波长的四阵元线阵和面阵,给出了仿真结果。并通过系统的对天测试,给出了实测数据,从而说明了共轭梯度法的优点和适用场景。结果表明:相比于最陡下降法,共轭梯度算法可以在不大于阵元数量的迭代次数下快速收敛到与直接求逆算法几乎相同的干扰压制效果。FPGA实测中,在62 MHz时钟频率,3000快拍条件下权重更新时间小于48 us。针对单个和三个20 MHz宽带干扰,分别可以达到80 dB和65 dB左右的抗干扰性能。更多还原

【Abstract】 When the Beidou navigation signals arrive at the user receivers, it is quite weak and highly susceptible to intentional or unintentional interferences, resulting in significant positioning errors or even unable to positioning. The blind interference cancellation technologies represented by power inversion(PI) algorithm can suppress the interferences effectively by optimizing the weight coefficients of antenna array without the prior information of interferences, and improve the output signal to interference plus noise ratio(SINR). To achieve a tradeoff between the anti-interference performance and the implementation complexity, the System Generator-based PI algorithm is proposed to carrier out the development of digital system efficiently. By exploiting the parallel processing performance of field programmable gate array(FPGA), the anti-jamming system is realized by direct inversion algorithm, steepest descent algorithm and conjugate gradient algorithm based on minimum mean square error(MMSE) criterion. Simulation and measurement results using four-antenna array with half wavelength spacing show that compared with the steepest descent method, the conjugate gradient algorithm can converge to the same performance of interference suppression quickly under the number of iterations no more than the number of array elements, which explains the advantages and applicable scenarios of the conjugate gradient method. In FPGA implementation, the weight update time is less than 48 us under the condition of 62 MHz clock frequency and 3000 snapshots. For single and three 20 MHz wideband interferences, it can achieve an anti-interference performance of about 80 dB and 65 dB, respectively.更多还原